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Struct iced_x86::DecoderOptions

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pub struct DecoderOptions;
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Decoder options

Implementations

No option is enabled

Disable some checks for invalid encodings of instructions, eg. most instructions can’t use a LOCK prefix so if one is found, they’re decoded as Code::INVALID unless this option is enabled.

AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS, UD0 has no modr/m byte, decode LOCK MOV CR. The AMD decoder can still decode Intel instructions.

Decode opcodes 0F0D and 0F18-0F1F as reserved-nop instructions (eg. Code::Reservednop_rm32_r32_0F1D)

Decode UMOV instructions

Decode XBTS/IBTS

Decode 0FA6/0FA7 as CMPXCHG

Decode some old removed FPU instructions (eg. FRSTPM)

Decode PCOMMIT

Decode 286 STOREALL/LOADALL (0F04 and 0F05)

Decode 386 LOADALL

Decode CL1INVMB

Decode MOV r32,tr and MOV tr,r32

Decode JMPE instructions

Don’t decode PAUSE, decode NOP instead

Don’t decode WBNOINVD, decode WBINVD instead

Decode undocumented Intel RDUDBG and WRUDBG instructions

Don’t decode TZCNT, decode BSF instead

Don’t decode LZCNT, decode BSR instead

Don’t decode LAHF and SAHF in 64-bit mode

Decode MPX instructions

Decode most Cyrix instructions: FPU, EMMI, SMM, DDI

Decode Cyrix SMINT 0F7E (Cyrix 6x86 or earlier)

Decode Cyrix DMI instructions (AMD Geode GX/LX)

Decode Centaur ALTINST

Decode Intel Knights Corner instructions (requires the mvex feature)

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Calls U::from(self).

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The type returned in the event of a conversion error.
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The type returned in the event of a conversion error.
Performs the conversion.