#[repr(simd)]pub struct Simd<T, const LANES: usize>(_)
where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount;
Expand description
A SIMD vector of LANES
elements of type T
.
Implementations
Horizontal bitwise “and”. Returns the cumulative bitwise “and” across the lanes of the vector.
Horizontal bitwise “or”. Returns the cumulative bitwise “or” across the lanes of the vector.
Horizontal bitwise “xor”. Returns the cumulative bitwise “xor” across the lanes of the vector.
impl<T, const LANES: usize> Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
Reverse the order of the lanes in the vector.
Rotates the vector such that the first OFFSET
elements of the slice move to the end
while the last LANES - OFFSET
elements move to the front. After calling rotate_lanes_left
,
the element previously in lane OFFSET
will become the first element in the slice.
Rotates the vector such that the first LANES - OFFSET
elements of the vector move to
the end while the last OFFSET
elements move to the front. After calling rotate_lanes_right
,
the element previously at index LANES - OFFSET
will become the first element in the slice.
Interleave two vectors.
Produces two vectors with lanes taken alternately from self
and other
.
The first result contains the first LANES / 2
lanes from self
and other
,
alternating, starting with the first lane of self
.
The second result contains the last LANES / 2
lanes from self
and other
,
alternating, starting with the lane LANES / 2
from the start of self
.
#![feature(portable_simd)]
let a = Simd::from_array([0, 1, 2, 3]);
let b = Simd::from_array([4, 5, 6, 7]);
let (x, y) = a.interleave(b);
assert_eq!(x.to_array(), [0, 4, 1, 5]);
assert_eq!(y.to_array(), [2, 6, 3, 7]);
RunDeinterleave two vectors.
The first result takes every other lane of self
and then other
, starting with
the first lane.
The second result takes every other lane of self
and then other
, starting with
the second lane.
#![feature(portable_simd)]
let a = Simd::from_array([0, 4, 1, 5]);
let b = Simd::from_array([2, 6, 3, 7]);
let (x, y) = a.deinterleave(b);
assert_eq!(x.to_array(), [0, 1, 2, 3]);
assert_eq!(y.to_array(), [4, 5, 6, 7]);
Runimpl<T, const LANES: usize> Simd<T, LANES> where
T: SimdElement + PartialEq<T>,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Simd<T, LANES> where
T: SimdElement + PartialEq<T>,
LaneCount<LANES>: SupportedLaneCount,
Test if each lane is equal to the corresponding lane in other
.
impl<T, const LANES: usize> Simd<T, LANES> where
T: SimdElement + PartialOrd<T>,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Simd<T, LANES> where
T: SimdElement + PartialOrd<T>,
LaneCount<LANES>: SupportedLaneCount,
Test if each lane is less than the corresponding lane in other
.
Test if each lane is greater than the corresponding lane in other
.
Test if each lane is less than or equal to the corresponding lane in other
.
impl<T, const LANES: usize> Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
Number of lanes in this vector.
Get the number of lanes in this vector.
Construct a SIMD vector by setting all lanes to the given value.
Returns an array reference containing the entire SIMD vector.
Returns a mutable array reference containing the entire SIMD vector.
Converts an array to a SIMD vector.
Converts a SIMD vector to an array.
Converts a slice to a SIMD vector containing slice[..LANES]
Panics
from_slice
will panic if the slice’s len
is less than the vector’s Simd::LANES
.
Reads from potentially discontiguous indices in slice
to construct a SIMD vector.
If an index is out-of-bounds, the lane is instead selected from the or
vector.
Examples
let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];
let idxs = Simd::from_array([9, 3, 0, 5]);
let alt = Simd::from_array([-5, -4, -3, -2]);
let result = Simd::gather_or(&vec, idxs, alt); // Note the lane that is out-of-bounds.
assert_eq!(result, Simd::from_array([-5, 13, 10, 15]));
Runpub fn gather_or_default(
slice: &[T],
idxs: Simd<usize, LANES>
) -> Simd<T, LANES> where
T: Default,
pub fn gather_or_default(
slice: &[T],
idxs: Simd<usize, LANES>
) -> Simd<T, LANES> where
T: Default,
Reads from potentially discontiguous indices in slice
to construct a SIMD vector.
If an index is out-of-bounds, the lane is set to the default value for the type.
Examples
let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];
let idxs = Simd::from_array([9, 3, 0, 5]);
let result = Simd::gather_or_default(&vec, idxs); // Note the lane that is out-of-bounds.
assert_eq!(result, Simd::from_array([0, 13, 10, 15]));
Runpub fn gather_select(
slice: &[T],
enable: Mask<isize, LANES>,
idxs: Simd<usize, LANES>,
or: Simd<T, LANES>
) -> Simd<T, LANES>
pub fn gather_select(
slice: &[T],
enable: Mask<isize, LANES>,
idxs: Simd<usize, LANES>,
or: Simd<T, LANES>
) -> Simd<T, LANES>
Reads from potentially discontiguous indices in slice
to construct a SIMD vector.
The mask enable
s all true
lanes and disables all false
lanes.
If an index is disabled or is out-of-bounds, the lane is selected from the or
vector.
Examples
let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];
let idxs = Simd::from_array([9, 3, 0, 5]);
let alt = Simd::from_array([-5, -4, -3, -2]);
let enable = Mask::from_array([true, true, true, false]); // Note the mask of the last lane.
let result = Simd::gather_select(&vec, enable, idxs, alt); // Note the lane that is out-of-bounds.
assert_eq!(result, Simd::from_array([-5, 13, 10, -2]));
Runpub unsafe fn gather_select_unchecked(
slice: &[T],
enable: Mask<isize, LANES>,
idxs: Simd<usize, LANES>,
or: Simd<T, LANES>
) -> Simd<T, LANES>
pub unsafe fn gather_select_unchecked(
slice: &[T],
enable: Mask<isize, LANES>,
idxs: Simd<usize, LANES>,
or: Simd<T, LANES>
) -> Simd<T, LANES>
Reads from potentially discontiguous indices in slice
to construct a SIMD vector.
The mask enable
s all true
lanes and disables all false
lanes.
If an index is disabled, the lane is selected from the or
vector.
Safety
Calling this function with an enable
d out-of-bounds index is undefined behavior
even if the resulting value is not used.
Examples
let vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];
let idxs = Simd::from_array([9, 3, 0, 5]);
let alt = Simd::from_array([-5, -4, -3, -2]);
let enable = Mask::from_array([true, true, true, false]); // Note the final mask lane.
// If this mask was used to gather, it would be unsound. Let's fix that.
let enable = enable & idxs.lanes_lt(Simd::splat(vec.len()));
// We have masked the OOB lane, so it's safe to gather now.
let result = unsafe { Simd::gather_select_unchecked(&vec, enable, idxs, alt) };
assert_eq!(result, Simd::from_array([-5, 13, 10, -2]));
RunWrites the values in a SIMD vector to potentially discontiguous indices in slice
.
If two lanes in the scattered vector would write to the same index
only the last lane is guaranteed to actually be written.
Examples
let mut vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];
let idxs = Simd::from_array([9, 3, 0, 0]);
let vals = Simd::from_array([-27, 82, -41, 124]);
vals.scatter(&mut vec, idxs); // index 0 receives two writes.
assert_eq!(vec, vec![124, 11, 12, 82, 14, 15, 16, 17, 18]);
RunWrites the values in a SIMD vector to multiple potentially discontiguous indices in slice
.
The mask enable
s all true
lanes and disables all false
lanes.
If an enabled index is out-of-bounds, the lane is not written.
If two enabled lanes in the scattered vector would write to the same index,
only the last lane is guaranteed to actually be written.
Examples
let mut vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];
let idxs = Simd::from_array([9, 3, 0, 0]);
let vals = Simd::from_array([-27, 82, -41, 124]);
let enable = Mask::from_array([true, true, true, false]); // Note the mask of the last lane.
vals.scatter_select(&mut vec, enable, idxs); // index 0's second write is masked, thus omitted.
assert_eq!(vec, vec![-41, 11, 12, 82, 14, 15, 16, 17, 18]);
Runpub unsafe fn scatter_select_unchecked(
self,
slice: &mut [T],
enable: Mask<isize, LANES>,
idxs: Simd<usize, LANES>
)
pub unsafe fn scatter_select_unchecked(
self,
slice: &mut [T],
enable: Mask<isize, LANES>,
idxs: Simd<usize, LANES>
)
Writes the values in a SIMD vector to multiple potentially discontiguous indices in slice
.
The mask enable
s all true
lanes and disables all false
lanes.
If two enabled lanes in the scattered vector would write to the same index,
only the last lane is guaranteed to actually be written.
Safety
Calling this function with an enabled out-of-bounds index is undefined behavior, and may lead to memory corruption.
Examples
let mut vec: Vec<i32> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];
let idxs = Simd::from_array([9, 3, 0, 0]);
let vals = Simd::from_array([-27, 82, -41, 124]);
let enable = Mask::from_array([true, true, true, false]); // Note the mask of the last lane.
// If this mask was used to scatter, it would be unsound. Let's fix that.
let enable = enable & idxs.lanes_lt(Simd::splat(vec.len()));
// We have masked the OOB lane, so it's safe to scatter now.
unsafe { vals.scatter_select_unchecked(&mut vec, enable, idxs); }
// index 0's second write is masked, thus was omitted.
assert_eq!(vec, vec![-41, 11, 12, 82, 14, 15, 16, 17, 18]);
RunHorizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
Horizontal maximum. Returns the maximum lane in the vector.
Horizontal minimum. Returns the minimum lane in the vector.
Horizontal add. Returns the sum of the lanes of the vector.
Horizontal multiply. Returns the product of the lanes of the vector.
Horizontal maximum. Returns the maximum lane in the vector.
Returns values based on equality, so a vector containing both 0.
and -0.
may
return either. This function will not return NaN
unless all lanes are NaN
.
Horizontal minimum. Returns the minimum lane in the vector.
Returns values based on equality, so a vector containing both 0.
and -0.
may
return either. This function will not return NaN
unless all lanes are NaN
.
Horizontal add. Returns the sum of the lanes of the vector.
Horizontal multiply. Returns the product of the lanes of the vector.
Horizontal maximum. Returns the maximum lane in the vector.
Returns values based on equality, so a vector containing both 0.
and -0.
may
return either. This function will not return NaN
unless all lanes are NaN
.
Horizontal minimum. Returns the minimum lane in the vector.
Returns values based on equality, so a vector containing both 0.
and -0.
may
return either. This function will not return NaN
unless all lanes are NaN
.
Lanewise saturating absolute value, implemented in Rust. As abs(), except the MIN value becomes MAX instead of itself.
Examples
let xs = Simd::from_array([MIN, -2, 0, 3]);
let unsat = xs.abs();
let sat = xs.saturating_abs();
assert_eq!(unsat, Simd::from_array([MIN, 2, 0, 3]));
assert_eq!(sat, Simd::from_array([MAX, 2, 0, 3]));
RunLanewise saturating negation, implemented in Rust. As neg(), except the MIN value becomes MAX instead of itself.
Examples
let x = Simd::from_array([MIN, -2, 3, MAX]);
let unsat = -x;
let sat = x.saturating_neg();
assert_eq!(unsat, Simd::from_array([MIN, 2, -3, MIN + 1]));
assert_eq!(sat, Simd::from_array([MAX, 2, -3, MIN + 1]));
RunLanewise saturating absolute value, implemented in Rust. As abs(), except the MIN value becomes MAX instead of itself.
Examples
let xs = Simd::from_array([MIN, -2, 0, 3]);
let unsat = xs.abs();
let sat = xs.saturating_abs();
assert_eq!(unsat, Simd::from_array([MIN, 2, 0, 3]));
assert_eq!(sat, Simd::from_array([MAX, 2, 0, 3]));
RunLanewise saturating negation, implemented in Rust. As neg(), except the MIN value becomes MAX instead of itself.
Examples
let x = Simd::from_array([MIN, -2, 3, MAX]);
let unsat = -x;
let sat = x.saturating_neg();
assert_eq!(unsat, Simd::from_array([MIN, 2, -3, MIN + 1]));
assert_eq!(sat, Simd::from_array([MAX, 2, -3, MIN + 1]));
RunLanewise saturating absolute value, implemented in Rust. As abs(), except the MIN value becomes MAX instead of itself.
Examples
let xs = Simd::from_array([MIN, -2, 0, 3]);
let unsat = xs.abs();
let sat = xs.saturating_abs();
assert_eq!(unsat, Simd::from_array([MIN, 2, 0, 3]));
assert_eq!(sat, Simd::from_array([MAX, 2, 0, 3]));
RunLanewise saturating negation, implemented in Rust. As neg(), except the MIN value becomes MAX instead of itself.
Examples
let x = Simd::from_array([MIN, -2, 3, MAX]);
let unsat = -x;
let sat = x.saturating_neg();
assert_eq!(unsat, Simd::from_array([MIN, 2, -3, MIN + 1]));
assert_eq!(sat, Simd::from_array([MAX, 2, -3, MIN + 1]));
RunLanewise saturating absolute value, implemented in Rust. As abs(), except the MIN value becomes MAX instead of itself.
Examples
let xs = Simd::from_array([MIN, -2, 0, 3]);
let unsat = xs.abs();
let sat = xs.saturating_abs();
assert_eq!(unsat, Simd::from_array([MIN, 2, 0, 3]));
assert_eq!(sat, Simd::from_array([MAX, 2, 0, 3]));
RunLanewise saturating negation, implemented in Rust. As neg(), except the MIN value becomes MAX instead of itself.
Examples
let x = Simd::from_array([MIN, -2, 3, MAX]);
let unsat = -x;
let sat = x.saturating_neg();
assert_eq!(unsat, Simd::from_array([MIN, 2, -3, MIN + 1]));
assert_eq!(sat, Simd::from_array([MAX, 2, -3, MIN + 1]));
RunLanewise saturating absolute value, implemented in Rust. As abs(), except the MIN value becomes MAX instead of itself.
Examples
let xs = Simd::from_array([MIN, -2, 0, 3]);
let unsat = xs.abs();
let sat = xs.saturating_abs();
assert_eq!(unsat, Simd::from_array([MIN, 2, 0, 3]));
assert_eq!(sat, Simd::from_array([MAX, 2, 0, 3]));
RunLanewise saturating negation, implemented in Rust. As neg(), except the MIN value becomes MAX instead of itself.
Examples
let x = Simd::from_array([MIN, -2, 3, MAX]);
let unsat = -x;
let sat = x.saturating_neg();
assert_eq!(unsat, Simd::from_array([MIN, 2, -3, MIN + 1]));
assert_eq!(sat, Simd::from_array([MAX, 2, -3, MIN + 1]));
RunRounds toward zero and converts to the same-width integer type, assuming that the value is finite and fits in that type.
Safety
The value must:
- Not be NaN
- Not be infinite
- Be representable in the return type, after truncating off its fractional part
Rounds toward zero and converts to the same-width integer type, assuming that the value is finite and fits in that type.
Safety
The value must:
- Not be NaN
- Not be infinite
- Be representable in the return type, after truncating off its fractional part
Raw transmutation to an unsigned integer vector type with the same size and number of lanes.
Raw transmutation from an unsigned integer vector type with the same size and number of lanes.
Produces a vector where every lane has the absolute value of the
equivalently-indexed lane in self
.
Takes the reciprocal (inverse) of each lane, 1/x
.
Converts each lane from radians to degrees.
Converts each lane from degrees to radians.
Returns true for each lane if it has a positive sign, including
+0.0
, NaN
s with positive sign bit and positive infinity.
Returns true for each lane if it has a negative sign, including
-0.0
, NaN
s with negative sign bit and negative infinity.
Returns true for each lane if its value is NaN
.
Returns true for each lane if its value is positive infinity or negative infinity.
Returns true for each lane if its value is neither infinite nor NaN
.
Returns true for each lane if its value is subnormal.
Returns true for each lane if its value is neither neither zero, infinite,
subnormal, or NaN
.
Replaces each lane with a number that represents its sign.
1.0
if the number is positive,+0.0
, orINFINITY
-1.0
if the number is negative,-0.0
, orNEG_INFINITY
NAN
if the number isNAN
Returns each lane with the magnitude of self
and the sign of sign
.
If any lane is a NAN
, then a NAN
with the sign of sign
is returned.
Returns the minimum of each lane.
If one of the values is NAN
, then the other value is returned.
Returns the maximum of each lane.
If one of the values is NAN
, then the other value is returned.
Restrict each lane to a certain interval unless it is NaN.
For each lane in self
, returns the corresponding lane in max
if the lane is
greater than max
, and the corresponding lane in min
if the lane is less
than min
. Otherwise returns the lane in self
.
Raw transmutation to an unsigned integer vector type with the same size and number of lanes.
Raw transmutation from an unsigned integer vector type with the same size and number of lanes.
Produces a vector where every lane has the absolute value of the
equivalently-indexed lane in self
.
Takes the reciprocal (inverse) of each lane, 1/x
.
Converts each lane from radians to degrees.
Converts each lane from degrees to radians.
Returns true for each lane if it has a positive sign, including
+0.0
, NaN
s with positive sign bit and positive infinity.
Returns true for each lane if it has a negative sign, including
-0.0
, NaN
s with negative sign bit and negative infinity.
Returns true for each lane if its value is NaN
.
Returns true for each lane if its value is positive infinity or negative infinity.
Returns true for each lane if its value is neither infinite nor NaN
.
Returns true for each lane if its value is subnormal.
Returns true for each lane if its value is neither neither zero, infinite,
subnormal, or NaN
.
Replaces each lane with a number that represents its sign.
1.0
if the number is positive,+0.0
, orINFINITY
-1.0
if the number is negative,-0.0
, orNEG_INFINITY
NAN
if the number isNAN
Returns each lane with the magnitude of self
and the sign of sign
.
If any lane is a NAN
, then a NAN
with the sign of sign
is returned.
Returns the minimum of each lane.
If one of the values is NAN
, then the other value is returned.
Returns the maximum of each lane.
If one of the values is NAN
, then the other value is returned.
Restrict each lane to a certain interval unless it is NaN.
For each lane in self
, returns the corresponding lane in max
if the lane is
greater than max
, and the corresponding lane in min
if the lane is less
than min
. Otherwise returns the lane in self
.
Returns true for each positive lane and false if it is zero or negative.
Returns true for each negative lane and false if it is zero or positive.
Returns true for each positive lane and false if it is zero or negative.
Returns true for each negative lane and false if it is zero or positive.
Returns true for each positive lane and false if it is zero or negative.
Returns true for each negative lane and false if it is zero or positive.
Returns true for each positive lane and false if it is zero or negative.
Returns true for each negative lane and false if it is zero or positive.
Returns true for each positive lane and false if it is zero or negative.
Returns true for each negative lane and false if it is zero or positive.
Trait Implementations
Performs the +=
operation. Read more
impl<T, const LANES: usize> AsMut<[T; LANES]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> AsMut<[T; LANES]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> AsMut<[T]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> AsMut<[T]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> AsRef<[T; LANES]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> AsRef<[T; LANES]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> AsRef<[T]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> AsRef<[T]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Binary for Simd<T, LANES> where
T: SimdElement + Binary,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Binary for Simd<T, LANES> where
T: SimdElement + Binary,
LaneCount<LANES>: SupportedLaneCount,
impl<T, U, const LANES: usize> BitAndAssign<U> for Simd<T, LANES> where
T: SimdElement,
Simd<T, LANES>: BitAnd<U>,
LaneCount<LANES>: SupportedLaneCount,
<Simd<T, LANES> as BitAnd<U>>::Output == Simd<T, LANES>,
impl<T, U, const LANES: usize> BitAndAssign<U> for Simd<T, LANES> where
T: SimdElement,
Simd<T, LANES>: BitAnd<U>,
LaneCount<LANES>: SupportedLaneCount,
<Simd<T, LANES> as BitAnd<U>>::Output == Simd<T, LANES>,
Performs the &=
operation. Read more
impl<T, U, const LANES: usize> BitOrAssign<U> for Simd<T, LANES> where
T: SimdElement,
Simd<T, LANES>: BitOr<U>,
LaneCount<LANES>: SupportedLaneCount,
<Simd<T, LANES> as BitOr<U>>::Output == Simd<T, LANES>,
impl<T, U, const LANES: usize> BitOrAssign<U> for Simd<T, LANES> where
T: SimdElement,
Simd<T, LANES>: BitOr<U>,
LaneCount<LANES>: SupportedLaneCount,
<Simd<T, LANES> as BitOr<U>>::Output == Simd<T, LANES>,
Performs the |=
operation. Read more
impl<T, U, const LANES: usize> BitXorAssign<U> for Simd<T, LANES> where
T: SimdElement,
Simd<T, LANES>: BitXor<U>,
LaneCount<LANES>: SupportedLaneCount,
<Simd<T, LANES> as BitXor<U>>::Output == Simd<T, LANES>,
impl<T, U, const LANES: usize> BitXorAssign<U> for Simd<T, LANES> where
T: SimdElement,
Simd<T, LANES>: BitXor<U>,
LaneCount<LANES>: SupportedLaneCount,
<Simd<T, LANES> as BitXor<U>>::Output == Simd<T, LANES>,
Performs the ^=
operation. Read more
impl<T, const LANES: usize> Clone for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Clone for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Debug for Simd<T, LANES> where
T: SimdElement + Debug,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Debug for Simd<T, LANES> where
T: SimdElement + Debug,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Default for Simd<T, LANES> where
T: SimdElement + Default,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Default for Simd<T, LANES> where
T: SimdElement + Default,
LaneCount<LANES>: SupportedLaneCount,
Performs the /=
operation. Read more
impl<T, const LANES: usize> From<[T; LANES]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> From<[T; LANES]> for Simd<T, LANES> where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> From<Mask<T, LANES>> for Simd<T, LANES> where
T: MaskElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> From<Mask<T, LANES>> for Simd<T, LANES> where
T: MaskElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> From<Simd<T, LANES>> for [T; LANES] where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> From<Simd<T, LANES>> for [T; LANES] where
T: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Hash for Simd<T, LANES> where
T: SimdElement + Hash,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Hash for Simd<T, LANES> where
T: SimdElement + Hash,
LaneCount<LANES>: SupportedLaneCount,
impl<I, T, const LANES: usize> Index<I> for Simd<T, LANES> where
T: SimdElement,
I: SliceIndex<[T]>,
LaneCount<LANES>: SupportedLaneCount,
impl<I, T, const LANES: usize> Index<I> for Simd<T, LANES> where
T: SimdElement,
I: SliceIndex<[T]>,
LaneCount<LANES>: SupportedLaneCount,
impl<I, T, const LANES: usize> IndexMut<I> for Simd<T, LANES> where
T: SimdElement,
I: SliceIndex<[T]>,
LaneCount<LANES>: SupportedLaneCount,
impl<I, T, const LANES: usize> IndexMut<I> for Simd<T, LANES> where
T: SimdElement,
I: SliceIndex<[T]>,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> LowerExp for Simd<T, LANES> where
T: SimdElement + LowerExp,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> LowerExp for Simd<T, LANES> where
T: SimdElement + LowerExp,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> LowerHex for Simd<T, LANES> where
T: SimdElement + LowerHex,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> LowerHex for Simd<T, LANES> where
T: SimdElement + LowerHex,
LaneCount<LANES>: SupportedLaneCount,
Performs the *=
operation. Read more
impl<const LANES: usize> Neg for Simd<i64, LANES> where
i64: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<i64, LANES> where
i64: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<i32, LANES> where
i32: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<i32, LANES> where
i32: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<f64, LANES> where
f64: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<f64, LANES> where
f64: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<f32, LANES> where
f32: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<f32, LANES> where
f32: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<i8, LANES> where
i8: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<i8, LANES> where
i8: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<i16, LANES> where
i16: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<i16, LANES> where
i16: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<isize, LANES> where
isize: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Neg for Simd<isize, LANES> where
isize: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<u32, LANES> where
u32: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<u32, LANES> where
u32: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<i8, LANES> where
i8: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<i8, LANES> where
i8: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<usize, LANES> where
usize: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<usize, LANES> where
usize: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<u8, LANES> where
u8: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<u8, LANES> where
u8: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<u16, LANES> where
u16: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<u16, LANES> where
u16: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<u64, LANES> where
u64: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<u64, LANES> where
u64: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<i64, LANES> where
i64: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<i64, LANES> where
i64: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<i32, LANES> where
i32: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<i32, LANES> where
i32: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<isize, LANES> where
isize: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<isize, LANES> where
isize: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<i16, LANES> where
i16: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<const LANES: usize> Not for Simd<i16, LANES> where
i16: SimdElement,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Octal for Simd<T, LANES> where
T: SimdElement + Octal,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Octal for Simd<T, LANES> where
T: SimdElement + Octal,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Ord for Simd<T, LANES> where
T: SimdElement + Ord,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> Ord for Simd<T, LANES> where
T: SimdElement + Ord,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> PartialEq<Simd<T, LANES>> for Simd<T, LANES> where
T: SimdElement + PartialEq<T>,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> PartialEq<Simd<T, LANES>> for Simd<T, LANES> where
T: SimdElement + PartialEq<T>,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> PartialOrd<Simd<T, LANES>> for Simd<T, LANES> where
T: SimdElement + PartialOrd<T>,
LaneCount<LANES>: SupportedLaneCount,
impl<T, const LANES: usize> PartialOrd<Simd<T, LANES>> for Simd<T, LANES> where
T: SimdElement + PartialOrd<T>,
LaneCount<LANES>: SupportedLaneCount,
This method returns an ordering between self
and other
values if one exists. Read more
This method tests less than (for self
and other
) and is used by the <
operator. Read more
This method tests less than or equal to (for self
and other
) and is used by the <=
operator. Read more
This method tests greater than (for self
and other
) and is used by the >
operator. Read more
Performs the %=
operation. Read more
Performs the <<=
operation. Read more
Performs the >>=
operation. Read more
Performs the -=
operation. Read more