🔬 This is a nightly-only experimental API. (stdsimd #27731)
This is supported on target_arch="riscv64" only.
Expand description

Platform-specific intrinsics for the riscv64 platform.

See the module documentation for more details.

Functions

fence_iExperimental

Generates the FENCE.I instruction

hfence_gvmaExperimental

Hypervisor memory management fence for guest physical address and virtual machine

hfence_gvma_allExperimental

Hypervisor memory management fence for all virtual machines and guest physical addresses

Hypervisor memory management fence for guest physical address

Hypervisor memory management fence for given virtual machine

hfence_vvmaExperimental

Hypervisor memory management fence for given guest virtual address and guest address space

hfence_vvma_allExperimental

Hypervisor memory management fence for all guest address spaces and guest virtual addresses

Hypervisor memory management fence for given guest address space

Hypervisor memory management fence for given guest virtual address

hinval_gvmaExperimental

Invalidate hypervisor translation cache for guest physical address and virtual machine

hinval_gvma_allExperimental

Invalidate hypervisor translation cache for all virtual machines and guest physical addresses

Invalidate hypervisor translation cache for guest physical address

Invalidate hypervisor translation cache for given virtual machine

hinval_vvmaExperimental

Invalidate hypervisor translation cache for given guest virtual address and guest address space

hinval_vvma_allExperimental

Invalidate hypervisor translation cache for all guest address spaces and guest virtual addresses

Invalidate hypervisor translation cache for given guest address space

Invalidate hypervisor translation cache for given guest virtual address

hlv_bExperimental

Loads virtual machine memory by signed byte integer

hlv_buExperimental

Loads virtual machine memory by unsigned byte integer

hlv_dExperimental

Loads virtual machine memory by unsigned double integer

hlv_hExperimental

Loads virtual machine memory by signed half integer

hlv_huExperimental

Loads virtual machine memory by unsigned half integer

hlv_wExperimental

Loads virtual machine memory by signed word integer

hlv_wuExperimental

Loads virtual machine memory by unsigned word integer

hlvx_huExperimental

Accesses virtual machine instruction by unsigned half integer

hlvx_wuExperimental

Accesses virtual machine instruction by unsigned word integer

hsv_bExperimental

Stores virtual machine memory by byte integer

hsv_dExperimental

Stores virtual machine memory by double integer

hsv_hExperimental

Stores virtual machine memory by half integer

hsv_wExperimental

Stores virtual machine memory by word integer

nopExperimental

Generates the NOP instruction

pauseExperimental

Generates the PAUSE instruction

sfence_inval_irExperimental

Generates the SFENCE.INVAL.IR instruction

sfence_vmaExperimental

Supervisor memory management fence for given virtual address and address space

sfence_vma_allExperimental

Supervisor memory management fence for all address spaces and virtual addresses

sfence_vma_asidExperimental

Supervisor memory management fence for given address space

Supervisor memory management fence for given virtual address

sfence_w_invalExperimental

Generates the SFENCE.W.INVAL instruction

sinval_vmaExperimental

Invalidate supervisor translation cache for given virtual address and address space

sinval_vma_allExperimental

Invalidate supervisor translation cache for all address spaces and virtual addresses

sinval_vma_asidExperimental

Invalidate supervisor translation cache for given address space

Invalidate supervisor translation cache for given virtual address

wfiExperimental

Generates the WFI instruction