This is supported on
target_arch="riscv64"
only.Expand description
Supervisor memory management fence for given virtual address and address space
The fence orders only reads and writes made to leaf page table entries corresponding to
the virtual address in parameter vaddr
, for the address space identified by integer parameter
asid
. Accesses to global mappings are not ordered. The fence also invalidates all
address-translation cache entries that contain leaf page table entries corresponding to the
virtual address in parameter vaddr
and that match the address space identified by integer
parameter asid
, except for entries containing global mappings.