This is supported on
target_arch="riscv64"
only.Expand description
Invalidate hypervisor translation cache for given guest virtual address and guest address space
This instruction invalidates any address-translation cache entries that an
HFENCE.VVMA
instruction with the same values of vaddr
and asid
would invalidate.
This fence specifies a single guest virtual address, and a single guest address-space identifier.