This is supported on
target_arch="riscv64"
only.Expand description
Hypervisor memory management fence for guest physical address and virtual machine
Guarantees that any previous stores already visible to the current hart are ordered before all implicit reads by that hart done for G-stage address translation for instructions that follow the HFENCE.GVMA.
This fence specifies a single guest physical address, shifted right by 2 bits, and a single virtual machine by virtual machine identifier (VMID).